1. Field of the Invention
The present invention relates to semiconductor fabrication techniques, and more particularly to techniques for fabricating dynamic random access memories (DRAM).
2. Description of the Background
A DRAM array is comprised of individual memory cells arranged in columns and rows on a lightly-doped silicon substrate. Each cell has a field-effect access transistor and a storage capacitor. The capacitor, which is directly connected to the transistor""s source or storage node, may be charged and discharged through the transistor""s channel. Transistor gates and gate interconnects within an array row are formed from a ribbon of conductive material which runs the length of the row. That conductive ribbon is known as a rowline. Between consecutive transistor gate within a row, the rowline traverses a field oxide region. In active areas of the array (locations where the rowline functions as a gate), the rowline is insulated from the substrate by a layer of gate oxide. When voltage is applied to each rowline through a driver transistor, all the transistors in the row are turned on. The access node of each transistor is connected to a columnar bit line. To determine the capacitor charge value (which may be equated with either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d binary value), a column sense amp at the end of the bit line compares the capacitor charge to a reference voltage.
The speed of a dynamic random access memory is dependent on a number of factors. One of the primary factors is access speed, i.e., the speed at which a rowline can turn on the transistors of the cells along a row. Rowline access speed is inversely proportional to the rowline""s resistance multiplied by its capacitance, i.e., an RC time constant. In other words, an increase in either the resistance of the capacitance of the rowline will degrade access speed. The reduction of rowline resistance is easily achieved. In fact, current DRAM designs typically utilize rowlines constructed from conductively-doped polycrystalline silicon (hereinafter xe2x80x9cPolysiliconxe2x80x9d) that has been silicided with a refractory metal such as titanium, platinum, palladium, cobalt, or tungsten. The resistance of a silicided, conductively-doped polysilicon is generally within the range of 5-25 ohms per square, whereas the resistance of titanium silicided conductively-doped polysilicon, for example, is approximately 2 ohms per square.
The reduction of rowline capacitance, however, is more problematic. Rowline capacitance is roughly equal to the summation of the polysilicon gate-to-substrate capacitances, because the field oxide regions are relatively thick and capacitances of the word line over those regions is relatively minimal. Using most current production techniques, all transistors within a DRAM array (whether they be cell access transistors or transistors within the periphery) utilize a single thickness of gate oxide. To reduce rowline capacitance using such fabrication techniques, it would be necessary to increase the gate oxide layer thickness. Because capacitance is inversely proportional to dielectric layer thickness, a doubling of dielectric layer thickness should approximately halve rowline capacitance. However, the drive current at maximum voltage for the peripheral, rowline driver transistors is decreased by the increase in dielectric layer thickness. Because of reduction in drive current will result in a reduction in rowline access speed, the gain in speed achieved through the reduction in rowline capacitance will be offset by the reduction in speed caused by decreased drive current.
A solution to the aforementioned problem is set forth in U.S. Pat. No. 5,057,499 entitled Process For Creating Two Thicknesses of Gate Oxide Within A Dynamic Random Access Memory. The invention disclosed therein achieves a net increase in rowline access speed by providing a process for creating DRAM memories having dual layers of gate oxide of different thicknesses. Peripheral driver transistors are constructed on top of a thin layer of gate oxide to optimize their performance whereas cell access transistors are constructed on top of a thicker layer of gate oxide to minimize rowline capacitance.
The process of U.S. Pat. No. 5,057,499 begins by thermally growing a first layer of gate oxide on a silicon substrate. The first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. During the growth of the second gate oxide layer, the thickness of the remaining fist oxide layer portions increases, but at a rate considerably slower than that at which new oxide initially forms on bare substrate regions. The resultant gate oxide layer, which then comprises regions of two different thicknesses, is used as a pad oxide layer during a conventional local oxidation of silicon (LOCOS) operation; nitride is deposited on the resultant gate oxide layer, masked, and etched to create regions devoid of nitride where field oxide regions will be grown. The field oxide regions are then thermally grown, and DRAM fabrication proceeds in a conventional manner.
While the invention of U.S. Pat. No. 5,057,449 provides a fabrication technique which enables gate oxide layers of different thicknesses to be fabricated, the need still exists, to create fabrication techniques that enable gate oxide layers of different thicknesses to be fabricated using fewer process steps and or fewer masks.
The present invention is directed to a fabrication technique in which dual gate oxide thicknesses are provided but with less steps and one less mask than is currently required. Beginning with a substrate on which a local oxidation of silicon process has been performed, i.e., a substrate as shown in FIG. 3, the process comprises the steps of stripping a pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
Starting with a bare substrate, the process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
According to one embodiment of the present invention, the step of striping the pad oxide and growing a sacrificial oxide layer can be eliminated if the pad oxide layer has the desired characteristics.
One advantage of the present invention is that the mask used as an implant mask to protect the area which will form the memory array is also used as an etch mask for etching the sacrificial oxide. That eliminates the need to create a separate etch mask and saves time by eliminating the steps associated with applying a separate etch mask. The diode characteristics are improved by the process of the present invention because the array area is protected during the implantation step for the peripheral devices. Static refresh times are improved. The process of the present invention also enables the thickness of the gate oxide to be tailored for the desired function thereby improving such characteristics as the subthreshold voltage and gate induced drain leakage. Those and other advantages and benefits will become apparent from the Description Of A Preferred Embodiment hereinbelow.